// Copyright (C) 1953-2022 NUDT
// Verilog module name - pdelay_req_read.v
// Version: V4.1.0.20221208
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module pdelay_req_read
(
	i_clk              ,
	i_rst_n            ,
   
	i_fifo_empty   ,
	o_fifo_rden    ,
	iv_fifo_rdata  ,
	
	i_data_ready   ,
	ov_data        ,
	o_data_wr
); 
// I/O
// clk & rst
input                  i_clk            ;
input                  i_rst_n          ; 
// pkt input
input                  i_fifo_empty  ;
output reg      	   o_fifo_rden   ;
input	   [8:0] 	   iv_fifo_rdata ;

input                  i_data_ready     ;
output reg [8:0]	   ov_data          ;
output reg	           o_data_wr        ;

//***************************************************
//               output schedule
//***************************************************
// internal reg&wire for state machine
reg  [3:0]  rv_cos_state;
reg  [6:0]  rv_cycle_cnt;
localparam  IDLE_S     = 4'd0,
            SCHEDULE_S = 4'd1,
            TRANSMIT_S = 4'd2;

always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n) begin
        o_fifo_rden         <= 1'b0;                    

        ov_data             <= 9'b0;
        o_data_wr           <= 1'b0;

		rv_cos_state        <= IDLE_S;
    end
    else begin
		case(rv_cos_state)
			IDLE_S:begin 
                ov_data             <= 9'b0;
                o_data_wr           <= 1'b0;              
                if(i_data_ready && (!i_fifo_empty))begin
                    o_fifo_rden     <= 1'b1; 
                    rv_cos_state    <= SCHEDULE_S; 
                end      
                else begin                  
                    o_fifo_rden         <= 1'b0;                                    
                    rv_cos_state        <= IDLE_S;
                end                
            end            
            SCHEDULE_S:begin
                ov_data      <= iv_fifo_rdata;
                o_data_wr    <= 1'b1;          
                rv_cos_state <= TRANSMIT_S; 
            end
            TRANSMIT_S:begin
                ov_data      <= iv_fifo_rdata;
                o_data_wr    <= 1'b1;          
                if(iv_fifo_rdata[8])begin//last cycle
                    o_fifo_rden         <= 1'b0; 
                    rv_cos_state        <= IDLE_S;
                end
                else begin
                    rv_cos_state <= TRANSMIT_S;
                end                
            end         
			default:begin               
                ov_data      <= 9'b0;
                o_data_wr    <= 1'b0;                
                o_fifo_rden  <= 1'b0; 
				rv_cos_state <= IDLE_S;	
			end
		endcase
    end
end	
endmodule